With a higher-resolution pattern transferred to a wafer, a foundry might not have to run a wafer through the EUV a second time to print the details needed which saves the foundry both time and money. At ASML’s conference call following its latest earnings report, Christophe Fouquet, chief business officer of ASML, said, “Regarding High-NA, or 0.55 NA EUV, we shipped our first system to a customer and this system is currently under installation. We started to ship the second system this month and its installation is also about to start.”
The recipient of the second High-NA EUV to ship is unknown. TSMC, the world’s largest foundry, is probably not the unnamed buyer of the latest High-NA EUV to be ordered. The foundry will have to buy one sometime, but it doesn’t seem that it is interested in making this purchase now. Meanwhile, ASML is believed to be working on the third-generation Hyper-NA EUV with a numerical aperture above .7.
When process nodes decline, so does the size of the transistors used with these chips. That means more transistors can fit inside these components and the higher a chip’s transistor count, the more powerful and/or energy-efficient a chip is. That’s why the High NA EUV is so important. As process nodes shrink and more transistors fit inside chips, the circuitry patterns etched on the silicon wafers need to be made using a finer resolution in order to shoehorn billions of transistors inside these components.
ASML’s Fouquet says, “The customer interest for our [High-NA] system lab is high as this system will help both our Logic and Memory customers prepare for High-NA insertion into their roadmaps. Relative to 0.33 NA, the 0.55 NA system provides finer resolution enabling an almost 3x increase in transistor density, at a similar productivity, in support of sub-2nm Logic and sub-10nm DRAM nodes.”